The present invention relates to a computer system, and more particularly to a method and apparatus for controlling data transfers between two interfaces of a computer system that have different data rates.
Often a computer system receives data from a source that is not synchronized to the local clock used by the computer system, for example peripheral buses often are not synchronized to the local system clock. Such a bus may be synchronized with respect to itself, yet its data may not have any simple relationship with the local system clock. Therefore, it is considered asynchronous with respect to the local system clock. Further, the asynchronous data transferred may be in random bursts or it may be at a rate that is not a simple multiple or fraction of the local system clock rate. Thus the computer system has the task of storing received data until it can be processed, which in this case includes matching data transfer rates between different parts of the computer system.
A known way to store data received from an asynchronous source is to receive the data into a first-in, first-out (FIFO) buffer memory circuit 200 as shown in FIG. 1. FIFO circuit 200 has a FIFO 202 which usually is an asynchronous type, referred to sometimes as a fall through type of FIFO. FIFO 202 can receive data from or transmit data to an interface 203 of one asynchronous device over data bus 204. Coordination of the asynchronous data transfer is accomplished by control signal transferred across control bus 206 to interface control logic 208. FIFO status signals regarding data transferred between the interface 203 and the FIFO 202 are transferred to interface control logic 208 by bus 209. Similarly, FIFO 202 can transmit data to or receive data from an interface 211 of a second device over data bus 210. Coordination of the data transferred between the interface 211 of the second device and the FIFO 202 is accomplished by control signals transferred across bus 212 to interface control logic 214. FIFO status signals regarding data transferred between the second device and the FIFO 202 are transferred to interface control logic 214 by bus 215.
If interface 203 is asynchronous with respect to the local clock, the FIFO 202 is a fall-through type, and control logic of interface 211 is implemented with synchronous logic, then the status signals from the FIFO 202 must be synchronized before being transmitted to the control logic of interface 211. Fall-through FIFOs tend to be layout sensitive, which means for high performance the layout must be carefully iterated and tested. Further, a fall-through FIFO introduces a data latency from the time the data is written to the FIFO 202 to the time that the data can be read from the FIFO 202. This data latency can be reduced by using high speed logic components, but it can never be eliminated.
If interface 203 is asynchronous with respect to the local clock, the FIFO 202 is a fall-through type, and control logic of interface 211 is implemented with asynchronous logic, then the interface signals from the FIFO 202 must be synchronized to the local clock from bus 212 before being transmitted. Such synchronization is necessary because data can be transferred between interface 203 and FIFO 202 at any time since it is controlled by a different clock. The time required for synchronization of status or interface signals could prevent interface 211 from operating at its full data rate. Additionally, since FIFO 202 is a fall-through type, it has the layout sensitivity and the latency problems mentioned above.
If the FIFO 202 is synchronous to the local clock, interface 203 is synchronous to its own local clock, then the data and status signals from interface 203 must be synchronized to the same clock signals that the FIFO 202 is synchronized with. A synchronous FIFO implementation tends not to be layout sensitive, so chip development time is reduced. The read latency of a synchronous FIFO is only one clock period instead of the component dependent 0+ to 2 clock periods of fall-through FIFOs. However, the synchronous implementation of the FIFO 202 in the circuit 200 inherently introduces a two clock period synchronization delay which can prevent interface 203 from operating at its full data rate.
In view of the limitations of the known FIFO circuit, it is an object of the present invention to provide a FIFO circuit that is interposed between two interfaces that are asynchronous with respect to each other and matches the full operating data rate of each.
It is another object of the present invention to provide a method for matching data rates of two interfaces that are asynchronous with respect to each other.